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ADF5902 Datasheet(PDF) 28 Page - Analog Devices |
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ADF5902 Datasheet(HTML) 28 Page - Analog Devices |
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28 / 39 page ![]() ADF5902 Data Sheet Rev. 0 | Page 28 of 39 DB31 DB30 DB27 DB28 DB29 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TDI TRC DS1 DS0 DO3 CONTROL BITS DO2 DO1 DO0 DW15 DW14 DW13 DW12 DW11 DW10 DW9 DW8 DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 C4(1) C3(1) C2(1) C1(0) C5(0) DEVIATION WORD DEVIATION OFFSET DEVIATION SEL DW14 DW15 ... ... ... ... ... ... ... ... ... ... ... ... DW1 DW0 DEVIATION WORD 00 0 0 0 00 0 1 1 00 1 0 2 00 1 1 3 11 1 1 –1 11 1 0 –2 11 0 1 – 1 0 0 0 –32,768 01 1 1 32,767 .. . . . .. . . . DO3 DO3 DO1 DO0 DEV OFFSET 00 00 0 00 01 1 00 10 2 . ... . . ... . 11 01 7 1 1 1 00 00 08 9 00 01 10 11 LOAD DEVIATION 0 LOAD DEVIATION 1 LOAD DEVIATION 2 LOAD DEVIATION 3 DEVIATION SEL DS1 DS0 RESERVED 0 00 0 DISABLED 1 ENABLED TRC 0CLK DIV 1 TDI Tx_DATA INV TX RAMP CLK Tx_DATA PIN 3 Figure 39. Register 14 (R14) REGISTER 14 Control Bits With Bits[C5:C1] set to 01110, Register R14 is programmed. Figure 39 shows the input data format for programming this register. Reserved Bits[DB29:DB27] are reserved and must be set as shown in Figure 39. TX_DATA Invert When Bit DB31 is set to 0, events triggered by TX_DATA occur on the rising edge of the TX_DATA pulse. When Bit DB31 is set to 1, events triggered by TX_DATA occur on the falling edge of the TX_DATA pulse. TX_DATA Ramp Clock When Bit DB30 is set to 0, the clock divider clock is used to clock the ramp. When Bit DB30 is set to 1, the TX_DATA pin is used to clock the ramp. Deviation Select Bits[DB26:DB25] select the deviation word to be loaded (see Figure 39). 4-Bit Deviation Offset Word Bits DB[24:21] determine the deviation offset word. The deviation offset word affects the deviation resolution (see the Ramp and Modulation section). 16-Bit Deviation Word Bits[DB20:DB5] determine the signed deviation word in twos complement format. The deviation word defines the deviation step (see the Ramp and Modulation section). |
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