ADF5902

Data Sheet

Rev. 0 | Page 18 of 39

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

00

0

0

0

0

0

00

CONTROL

BITS

0

0

0

0

0

1

0

AS

AA0 AA0

AC7

AC6

AC5 AC4 AC3 AC2 AC1 AC0

C4(0) C3(0) C2(1) C1(0)

RESERVED

ADC CLOCK DIVIDER

ADC

AVERAGE

C5(0)

AC7

AC6

AC1

AC0

ADC CLOCK DIVIDER

00

01

1

00

10

2

..

..

.

..

..

.

..

..

.

11

00

124

11

01

125

11

10

126

11

11

127

.

.

.

.

.

.

.

.

.

.

AS

0

1

ADC START

START ADC CONVERSION

NORMAL OPERATION

AA1

AA0

ADC AVERAGE

00

1

01

2

10

3

11

4

Figure 26. Register 2 (R2)

REGISTER 2

Control Bits

With Bits[C5:C1] set to 00010, Register R2 is programmed.

Figure 26 shows the input data format for programming this

register.

Reserved

Bits[DB31:DB16] are reserved and must be set as shown in

Figure 26.

ADC Start

Bit DB15 starts the ADC conversion. Setting this bit to 1 starts

an ADC conversion.

ADC Average

Bits[DB14:DB13] program the ADC average, which is the

number of averages of the ADC output (see Figure 26).

ADC Clock Divider

Bits[DB12:DB5] program the clock divider, which is used as the

sampling clock for the ADC (see Figure 26). The output of the

R divider block clocks the ADC clock divider. Program a

divider value to ensure the ADC sampling clock is 1 MHz.