ADF5902 datasheet(23/39 Pages) AD

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Data Sheet

ADF5902

Rev. 0 | Page 23 of 39

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

CONTROL

BITS

RD2

R4R3

R2R1

C4(0) C3(1) C2(1) C1(1)

C5(0)

RESERVED

R DIVIDER

R DIVIDER (R)

DISABLED

ENABLED

RD2

0DISABLED

ENABLED

REF

DOUBLER

RDIV2

MASTER RESET

ENABLED

DISABLED

DBR

CLOCK DIVIDER

C1D11 C1D10

.......... C1D2 C1D0

..........

4092

..........

4093

..........

4094

.........

4095

C1D11C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0

DBR1

CLOCK DIVIDER (CLK 1)

1DBR = DOUBLE-BUFFERED REGISTER.

Figure 31. Register 7 (R7)

Control Bits

With Bits[C5:C1] set to 00111, Register R7 is programmed.

Figure 31 shows the input data format for programming

this register.

Reserved

Bits[DB31:DB26] are reserved and must be set as shown in

Figure 31.

Master Reset

Bit DB25 provides a master reset bit for the device. Setting this

bit to 1 performs a reset of the device and all register maps.

Setting this bit to 0 returns the device to normal operation.

Clock Divider

Bits[DB23:DB12] controls the clock divider (CLK1) value (see

Figure 31). The CLK1 value sets a divider for the VCO frequency

calibration. Load the divider such that PFD frequency (fPFD)/

CLK1 is less than or equal to 25 kHz.

For example, for fPFD = 50 MHz, set CLK1 = 2048 so that fPFD/

CLK1 < 25 kHz.

The CLK1 value is also used to determine the duration of the

time step in ramp mode. See the Ramp and Modulation section

for more information.

Divide by 2 (RDIV2)

Setting the DB11 bit to 1 inserts a divide by 2 toggle flip flop

between the R counter and VCO calibration block.

Reference Doubler

Setting DB10 to 0 feeds the REFIN signal directly to the 5-bit

R counter, disabling the doubler. Setting this bit to 1 multiplies

the REFIN frequency by a factor of 2 before the REFIN signal is

fed to the 5-bit R counter. When the doubler is disabled, the

REFIN falling edge is the active edge at the PFD input to the

fractional synthesizer. When the doubler is enabled, both the

rising and falling edges of REFIN become active edges at the

PFD input.

When the reference doubler is enabled, for optimum phase

noise performance, it is recommended to only use charge pump

current settings of 0b0000 to 0b0111, that is, 0.28 mA to 2.24 mA

in Register 12. In this case, the best practice is to design the loop

filter for a charge pump current of 1.12 mA or 1.4 mA and then

use the programmable charge pump current to adjust the

frequency response.

The maximum allowable REFIN frequency when the doubler is

enabled is 50 MHz.

5-Bit R Divider

The 5-bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the VCO calibration block. Division ratios from 1 to 31 are

allowed.

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