ADF5902 datasheet(33/39 Pages) AD

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Data Sheet

ADF5902

Rev. 0 | Page 33 of 39

TEMPERATURE SENSOR

The ADF5902 has an on-chip temperature sensor that can be

accessed on the ATEST pin or as a digital word on DOUT

following an ADC conversion. The temperature sensor operates

over the full operating temperature range of −40°C to +105°C.

The accuracy can be improved by performing a one-point

calibration at room temperature and storing the result in

memory.

With the temperature sensor on the analog test bus and test bus

connected to the ATEST pin (Register 4 set to 0x0000A064), the

ATEST voltage can be converted to temperature with the

following equation:





GAIN

OFF

ATEST

Temperatur





(

(3)

where:

VATEST is the voltage on the ATEST pin.

VOFF = 0.699 V, the offset voltage.

VGAIN = 6.4 × 10−3, the voltage gain.

The temperature sensor result can be converted to a digital

word with the ADC and readback on DOUT with the following

sequence:

Write 0x00012064 to Register R4 to connect the analog test

bus to the ADC and the temperature sensor to the analog

test bus.

Write 0x0002A802 to Register R2 to start the ADC

conversion.

Write 0x0189FAC3 to Register R3 to set the ADC output

data to DOUT.

Read back DOUT.

Write 0x00002064 to Register R4 to reset Register R4 to the

initial value.

Write 0x00020642 to Register R2 to reset Register R2 to the

initial value.

Convert the DOUT word to temperature with the following

equation:









GAIN

OFF

LSB

ADC

Temperatur







(

(4)

where:

ADC is the ADC code read back on DOUT.

VLSB = 7.33 mV, the ADC LSB voltage.

VOFF = 0.699 V, the offset voltage.

VGAIN = 6.4 × 10−3, the voltage gain.

RF SYNTHESIS: A WORKED EXAMPLE

The following equation governs how to program the ADF5902:

RFOUT = (INT + (FRAC/225)) × fREF × 2

(5)

where:

RFOUT is the RF frequency output.

INT is the integer division factor.

FRAC is the fractionality.

fREF = REFIN × ((1 + D)/(R × (1 + T)))

(6)

where:

REFIN is the reference frequency input.

D is the reference doubler bit, DB10 in Register R7 (0 or 1).

R is the reference division factor.

T is the reference divide by 2 bit, DB11 in Register R7 (0 or 1).

For example, in a system where a 24.125 GHz RF frequency

output (RFOUT) is required and a 100 MHz reference frequency

input (REFIN) is available, fREF is set to 50 MHz.

From Equation 6,

fREF = (100 MHz × (1 + 0)/(1 × (1 + 1)) = 50 MHz

From Equation 5,

24.125 GHz = 50 MHz × (N + FRAC/225) × 2

Calculating the N and FRAC values,

N = int(RFOUT/(fREF × 2)) = 241

FRAC = FMSB × 213 + FLSB

FMSB = int(((RFOUT/(fREF × 2)) − N) × 212) = 1024

FLSB = int(((((RFOUT/(fREF × 2)) − N) × 212) − FMSB) × 213) = 0

where:

FMSB is the 12-bit MSB FRAC value in Register R5.

FLSB is the 13-bit LSB FRAC value in Register R6.

int() makes an integer of the argument in parentheses.

REFERENCE DOUBLER

The on-chip reference doubler allows the input reference signal to

be doubled. This doubling is useful for increasing the PFD compar-

ison frequency. Doubling the PFD frequency typically improves

the noise performance of the system by 3 dB.

ADF5902 Datasheet(PDF) 33 Page - Analog Devices

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