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ADF5902 Datasheet(PDF) 4 Page - Analog Devices

Part # ADF5902
Description  24 GHz, ISM Band, Multichannel FMCW Radar Transmitter
PDF  39 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF5902 Datasheet(HTML) 4 Page - Analog Devices

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ADF5902
Data Sheet
Rev. 0 | Page 4 of 39
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor, Fractional-N
Mode3
−222
dBc/Hz
PLL loop bandwidth (BW) = 1 MHz
Normalized 1/f Noise (PN1_f)4
−120
dBc/Hz
Measured at 10 kHz offset, normalized to 1 GHz
TEMPERATURE SENSOR
Analog Accuracy
±5
°C
Following one point calibration
Digital Accuracy
±5
°C
Following one point calibration
Sensitivity
6.4
mV/°C
ANALOG-TO-DIGITAL CONVERTER (ADC)
Resolution
8
Bits
Integral Nonlinearity (INL)
±1
LSB
Differential Nonlinearity (DNL)
±1
LSB
Least Significant Bit (LSB)
7.4
mV
REFIN CHARACTERISITICS
REFIN Input Frequency
10
260
MHz
−5 dBm minimum to +9 dBm maximum biased
at AHI/2 (ac coupling ensures 1.8 ÷ 2 bias); for
frequencies < 10 MHz, use a dc-coupled, CMOS-
compatible square wave with a slew rate > 25 V/μs
REFIN Input Capacitance2
1.2
pF
REFIN Input Current
±100
μA
LOGIC INPUTS
Input Voltage
High (VIH)
1.4
V
Low (VIL)
0.6
V
Input Current (IINH, IINL)
±1
μA
Input Capacitance (CIN)2
10
pF
LOGIC OUTPUTS
Output Voltage
High (VOH)5
DVDD −
0.4
V
Low (VOL)
0.4
V
Output Current
High (IOH)
500
μA
Low (IOL)
500
μA
1 Following the initialization sequence described in the Initialization Sequence section, TA = 25°C, AHI = 3.3 V, fREFIN = 100 MHz, and RF = 24.025 GHz.
2 Guaranteed by design. Sample tested to ensure compliance.
3 This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(fPFD) + 20 logN) to calculate
in-band phase noise performance as seen at the VCO output.
4 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at an offset frequency (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
5 DVDD selected from the IO level bit (Bit DB11 in Register 3).



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