HD64F2145 datasheet(214/829 Pages) RENESAS

214 / 829 page

Rev. 2.0, 08/02, page 174 of 788

• P40/TMCI0/TxD2/IrTxD

The pin function is switched as shown below according to the combination of the TE bit in

SCR of SCI_2 and the P40DDR bit.

P40DDR

—

P40

input pin

P40

output pin

TxD2/IrTxD

output pin

Pin Function

TMCI0 input pin*

Note:* When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR_0, this pin is

used as the TMCI0 input pin.

8.6

Port 5

Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_0 I/O pins, and the IIC_0 I/O pin. P52

and SCK0 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output. Port 5 has the

following registers.

• Port 5 data direction register (P5DDR)

• Port 5 data register (P5DR)

8.6.1

Port 5 Data Direction Register (P5DDR)

P5DDR specifies input or output for the pins of port 5 on a bit-by-bit basis.

Bit

Bit Name

Initial Value

R/W

Description

—

All 1

—

Reserved

The initial value must not be changed.

P52DDR

P51DDR

P50DDR

The corresponding port 5 pins are output ports

when P5DDR bits are set to 1, and input ports

when cleared to 0. As SCI_0 is initialized in

software standby mode, the pin states are

determined by the IIC_0 ICCR, P5DDR, and P5DR

specifications.

HD64F2145 Datasheet(PDF) 214 Page - Renesas Technology Corp

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