HD64F2145 datasheet(223/829 Pages) RENESAS

223 / 829 page

Rev. 2.0, 08/02, page 183 of 788

8.9.2

Port 8 Data Register (P8DR)

P8DR stores output data for the port 8 pins (P86 to P80).

Bit

Bit Name

Initial Value

R/W

Description

7—

—

Reserved

The initial value must not be changed.

P86DR

R/W

P85DR

R/W

P84DR

R/W

P83DR

R/W

P82DR

R/W

P81DR

R/W

P80DR

R/W

If a port 8 read is performed while P8DDR bits are

set to 1, the P8DR values are read directly,

regardless of the actual pin states. If a port 8 read

is performed while P8DDR bits are cleared to 0, the

pin states are read.

8.9.3

Pin Functions

• P86/,548/ SCK1/SCL1

The pin function is switched as shown below according to the combination of the CKE1 and

CKE0 bits in SCR of SCI_1, the C/

$ bit in SMR of SCI_1, the ICE bit in ICCR of IIC_1, and

the P86DDR bit.

ICE

CKE1

—

CKE0

—

P86DDR

——

P86

input pin

P86

output pin

SCK1

output pin

SCK1

output pin

SCK1

input pin

SCL1

I/O pin

Pin Function

,548 input pin*

Note:* When the IRQ5E bit in IER is set to 1, this pin is used as the

,548 input pin. When this pin

is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of SCI_1 and bit C/

$ in SMR of

SCI_1 must all be cleared to 0. When the P86 output pin and SCK1 output pin are set, the

output type is NMOS push-pull output. SCL1 is an NMOS-only output, and has direct bus

drive capability.

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