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HD64F2145 Datasheet(PDF) 225 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 225 Page - Renesas Technology Corp |
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225 / 829 page ![]() Rev. 2.0, 08/02, page 185 of 788 • P82/HIFSD/&/.581*2 The pin function is switched as shown below according to the combination of the HI12E and SDE bits in SYSCR2, the LPC3E to LPC1E bits in HICR0, and the P82DDR bit. LPC3E to LPC1E All 0 Not all 0 HI12E 0 1 0* 1 SDE — 0 1 — P82DDR 01 01 — 0* 1 Pin Function P82 input pin P82 output pin P82 input pin P82 output pin HIFSD input pin &/.581 I/O pin* 2 Notes: The HIFSD input pin and &/.581 I/O pin can only be used in mode 2 or 3 (EXPE = 0). 1. When at least one of bits LPC3E to LPC1E is set to 1, bits HI12E and P82DDR should be cleared to 0. 2. Not supported by the H8S/2148B. • P81/&65/GA20 The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the CS2E bit in SYSCR, the FGA20E bit in HICR, the FGA20E bit in HICR0, and the P81DDR bit. FGA20E (LPC) 01 HI12E 0 1 0* 1 FGA20E (XBS) —0 1 — CS2E — 0 1 — — P81DDR 0 1 0 1 — 0 1 0* 1 P81 input pin P81 output pin P81 input pin P81 output pin &65 input pin* 2 P81 input pin GA20 output pin GA20 output pin Pin Function GA20 input pin* 2 Notes: 1. When bit FGA20E is set to 1 in HICR0, bits HI12E and P81DDR should be cleared to 0. 2. The GA20 output pin and &65 input pin can only be used in mode 2 or 3 (EXPE = 0). |
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