HD64F2145 datasheet(232/829 Pages) RENESAS

232 / 829 page

Rev. 2.0, 08/02, page 192 of 788

8.11.1

Port A Data Direction Register (PADDR)

PADDR specifies input or output for the pins of port A on a bit-by-bit basis.

Bit

Bit Name

Initial Value

R/W

Description

PA7DDR

PA6DDR

PA5DDR

PA4DDR

PA3DDR

PA2DDR

PA1DDR

PA0DDR

In mode 1, 2 (EXPE = 0), or 3:

The corresponding port A pins are output ports

when PADDR bits are set to 1, and input ports

when cleared to 0.

In mode 2 (EXPE = 1):

The corresponding port A pins are address output

when PADDR bits are set to 1, and input ports

when cleared to 0. The port A pins changes from

the address I/O ports to output ports by setting the

IOSE bit to 1.

PA7 to PA2 pins are used as the keyboard buffer

controller I/O pins by setting the KBIOE bit to 1

regardless of the operating mode, while the I/O

direction according to PA7DDR to PA2DDR is

ignored.

PADDR has the same address as PAPIN, if read,

port A status is returned.

8.11.2

Port A Output Data Register (PAODR)

PAODR stores output data for port A.

Bit

Bit Name

Initial Value

R/W

Description

PA7ODR

R/W

PA6ODR

R/W

PA5ODR

R/W

PA4ODR

R/W

PA3ODR

R/W

PA2ODR

R/W

PA1ODR

R/W

PA0ODR

R/W

PAODR can always be read or written to,

regardless of the contents of PADDR.

HD64F2145 Datasheet(PDF) 232 Page - Renesas Technology Corp

HD64F2145 Datasheet(HTML) 232 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL