VSC7511 datasheet(46/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

Figure 8 •

SERDES6G Loopback Modes

3.4.3

Synchronous Ethernet

The SERDES6G block can recover the clock from the received data and apply the clock to either a per-

SerDes recovered clock output pin (SERDES6G_COMMON_CFG.RECO_SEL_A) or a common

recovered clock output pin that may be driven by another SerDes macros as well

(SERDES6G_COMMON_CFG.RECO_SEL_B). Note that only one macro should drive the common

recovered clock output pin at the same time.

In addition, it is possible to squelch the recovered clock if the associated PCS cannot detect valid data

(SERDES6G_COMMON_CFG.SE_AUTO_SQUELCH_A_ENA and

SERDES6G_COMMON_CFG.SE_AUTO_SQUELCH_B_ENA).

For more information about Synchronous Ethernet, see Layer 1 Timing, page 152.

3.4.4

SERDES6G Deserializer Configuration

The SERDES6G block includes digital control logic that interacts with the analog modules within the

block and compensates for the frequency offset between the received data and the internal high-speed

reference clock. To gain high jitter performance, the phase regulation is a PI-type regulator, whose

proportional (P) and integrative (I) characteristics can be independently configured.

The integrative part of the phase regulation loop is configured in

SERDES6G_DES_CFG.DES_PHS_CTRL. The limits of the integrator are programmable, allowing

different settings for the integrative regulation while guaranteeing that the proportional part still is

stronger than the integrative part. Integrative regulation compensates frequency modulation from DC up

to cut-off frequency. Frequencies greater than the cut-off frequency are compensated by the proportional

part.

The DES_BW_HYST register field controls the time constant of the integrator independently of the

proportional regulator. The range of DES_BW_HYST is programmable as follows:

•

Full rate mode = 3 to 7

•

Quarter-rate mode = 1 to 7

The lower the configuration setting the smaller the time-constant of the integrative regulation. For normal

operation, configure DES_BW_HYST to 5.

The cut-off-frequency is calculated to:

Tx (P/N)

Rx (P/N)

ESD

Input

Buffer

Output

Buffer

Equipment

Loop

Rx Path

Tx Path

ESD

Facility

Loop

Deserializer

Serializer

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