VSC7511 datasheet(47/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

fco = 1/(2 × PI × 128 × PLL period × 32 × 2^(DES_BW_HYST + 1 – DES_BW_ANA))

PLL period = 1/(n × data rate)

where, n=1 (full rate mode) or 4 (quarter-rate mode)

The integrative regulator can compensate a static frequency offset within the programmed limits down to

a remaining frequency error of below 4 ppm. In steady state, the integrator toggles between two values

around the exact value, and the proportional part of the phase regulation takes care of the remaining

phase error. The loop bandwidth for the proportional part of the phase regulation loop is controlled by

configuring SERDES6G_DES_CFG.SW.ANA.

The fastest loop bandwidth setting (lowest configuration value) results in a loop bandwidth that is equal to

the maximum frequency offset compensation capability. For improved jitter performance, use a setting

with sufficient margin to track the expected frequency offset rather than using the maximum frequency

offset. For example, if a 100 ppm offset is expected, use a setting that is four times higher than the offset.

The following table provides the limits for the frequency offset compensation. The values are theoretical

limits for input signals without jitter, because the actual frequency offset compensation capability is

dependent on the toggle rate of the input data and the input jitter. Note that only applicable configuration

values are listed. HRATE and QRATE are the configuration settings of

SERDES6G_COMMON_CFG.HRATE and SERDES6G_COMMON_CFG.QRATE.

In the event of an 180° phase jump of the incoming data signal, the sampling stage of the deserializer

may become stuck. To prevent this situation, the SERDES6G provides a 180° deadlock protection

mechanism (SERDES6G_DES_CFG.DES_MBTR_CTRL). If this mechanism is enabled, a small

frequency offset is applied to the phase regulation loop. The offset is sufficient to move the sampling

point out of the 180° deadlock region, while at the same time, small enough to allow the regulation loop to

compensate when the sample point is within the data eye.

3.4.5

SERDES6G Serializer Configuration

The serializer provides the ability to align the phase of the internal clock and data to a selected source

(SERDES6G_SER_CFG.SER_ENALI). The phase align logic is used when SERDES6G operates in the

facility loopback mode.

3.4.6

SERDES6G Input Buffer Configuration

The SERDES6G input buffer supports configurable options for:

•

Automatic input voltage offset compensation

•

Loss of signal detection

The input buffer is typically AC-coupled. As a result, the common-mode termination is switched off

(SERDES6G_IB_CFG1.IB_CTERM_ENA). In order to support type-2 loads (DC-coupling at 1.0 V

termination voltage) according to the OIF CEI specifications, common-mode termination must be

enabled.

Table 19 •

SERDES6G Loop Bandwidth

DES_BW_ANA

Limits when

HRATE = 1

QRATE = 0

Limits when

HRATE = 0

QRATE = 1

1953 ppm

977 ppm

488 ppm

244 ppm

122 ppm

61 ppm

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