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3.6 Clocks and startup

Two clock sources can be used to drive the system clock.



External oscillator clock (8MHz ~ 24MHz) (OCLK)



Internal 8MHz RC oscillator clock (RCLK)

One additional clock source



32.768KHz low speed external crystal which derives the real time clock.

There is a PLL

One PLL is integrated



Input clock range is from 8MHz to 24MHz



Frequency can be generated by M/N/OD registers. (refer register description)



Bypass option enabled

There are many generated clocks for independent operating with system clock



System clock (FCLK)



SSP0, SSP1 clock (SSPCLK)



UART0, UART1 clock (UARTCLK)



Two Timer clocks (TIMCLK0, TIMCLK1)



8ea PWM clocks (PWMCLK0 - PWMCLK7)



Real time clock (RTCCLK)



WDOG clock (WDOGCLK)



Random number generator clock (RNGCLK)

RNGCLK have only one source (pll output) and no prescaler

Some of the generated clocks turn off automatically when CPU enters sleep mode.



RNGCLK

Generate two Hardware TCPIP Clocks (MII_RXC, MII_TXC) are from external PADs.

Hardware TCPIP Clocks can be gated by register control.

All clocks generated from CRG can be monitored.

Figure 2. CRG block diagram

3.6.1

External Oscillator Clock

The External oscillator clock (OCLK) can be supplied with a 8 to 24 MHz crystal/ceramic

resonator oscillator. In the Typical application, Figure 3, ��

�� must be inserted in External

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