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1, 1.5, 2 Stop bits indicating that the frame is complete

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The USART interface uses a baud rate generator

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A status register (UART1_RISR)

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data registers (UART1DR)

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A baud rate register (UART1_IBRD,UART1_FBRD)

3.17 Synchronous Serial Port (SSP)

The SSP block is an IP provided by ARM (PL022 “PrimeCell® Synchronous Serial Port”).

Additional details about its functional blocks may be found in “ARM PrimeCell® Synchronous

Serial Port (PL022) Technical Reference Manual”.



The SSP is a master or slave interface that enables synchronous serial communication

with slave or master peripherals having one of the following:



A MOTOROLA SPI-compatible interface

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A TEXAS INSTRUMENTS synchronous serial interface

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A National Semiconductor MICROWIRE® interface.

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The SPI interface operates as a master or slave interface. It supports bit rates up to

20 MHz in master mode and up to 4 MHz in slave mode.

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Parallel-to-serial conversion on data written to an internal 16-bit wide, 8-

location deep transmit FIFO

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Serial-to-parallel conversion on received data, buffering it in a 16-bit wide, 8-location

deep receive FIFO

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Programmable data frame size from 4 to 16 bits

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Programmable clock bit rate and prescaler. The input clock may be divided by a factor

of 2 to 254 in steps of two to provide the serial output clock

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Programmable clock phase and polarity.

3.18 Random number generator (RNG)

RNG is a 32bit random number generator. RNG generates power on random number when

power on reset. RNG can run/stop by software. RNG seed value and polynomial of RNG can be

modified by software.

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32bit pseudo random number generator

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Formula of pseudo random number generator (polynomial) can be modified.



Seed value of random generator can be modified.

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Support power on reset random value.

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Random value can be obtains by control start/stop by software.

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