W7500P datasheet(20/38 Pages) WIZNET

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An internal clock source control based on missing/meeting durations. The COUNTFLAG

bit-field in the control and status register can be used to determine if an action

completed within a set duration, as part of a dynamic clock management control loop.

3.14.2

Pulse-Width Modulation (PWM)

The PWM consists a 8-channel 32-bit Timer/Counter driven by a programmable prescaler. The

function of the PWM is based on the basic Timer. Each timer and counter runs independently.

The PWM can be used to control the width of the pulse, formally the pulse duration, to

generate output waveform or to count the counter triggered by external input.

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Counter or Timer operation can use the peripheral clock, external clock source, or one

of the capture inputs as the clock source.

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Eight independent 32-bit Timer/Counter driven by a programmable 6 bits prescaler

runs as the PWM or standard timer if the PWM mode is not enabled.

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Eight PWM output waveforms.

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Each of Timer/Counter can have different or same clock source.

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Counter or timer operation.

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Eight capture registers that can take the timer value when an external input signal. A

capture event can generate an interrupt signal optionally.

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32-bit match register and limit register.

3.14.3

Dual timers

The dual timer consists two programmable 32-bit or 16-bit Free-running counters(FRCs) that

can generate interrupts when they reach 0. There are two dual timers and 4 FRCs. One dual

timers has one interrupt handler, resulting in two interrupts of timers. Also one dual timer has

one clock but two clock enable signals. Users can select one repetition modes one-shot or

wrapping mode, and wrapping mode consists free-running and periodic mode. Two FRCs are

one set so two FRCs has one clock, reset, and interrupt but each FRC has an individual clock

enable.

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One dual timer has two Free-Running Counters(FRCs).

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One dual timer has one interrupt handler and one clock.

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One dual timer has two clock enable signals.

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There are 2 dual timers.

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A 32-bit or a 16-bit down counter.

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One of the following repetition modes: one-shot and wrapping mode.

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One of the following wrapping modes: Free-running and periodic mode.

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There is a prescaler that can divide down the clock rate by 1, 16, or 256.

3.14.4

Watchdog timer

The watchdog is based on a 32-bit down-counter that is initialized from the Reload Register,

WDTLoad. The watchdog generates a regular interrupt depending on a programmed value. The

counter decreases by one on each positive clock edge of watchdog clock.

The watchdog monitors the interrupt and asserts a reset request signal when the counter

reaches 0 and the counter is stopped. On the next enabled watchdog clock edge, the counter

is reloaded from the WDTLoad Register and the countdown sequence continues. The watchdog

reasserts the reset signal if the interrupt is not cleared by the time the counter next reaches

The watchdog applies a reset to a system in the event of a software failure to provide a way

to recover from software crashes. Users can enable or disable the watchdog unit as required.

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32-bit down counter.

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