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NTP53X2 Datasheet(PDF) 101 Page - NXP Semiconductors |
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NTP53X2 Datasheet(HTML) 101 Page - NXP Semiconductors |
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101 / 133 page  NXP Semiconductors NTP53x2 NTAG 5 link - NFC Forum-compliant I2C bridge NTP53x2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 3.3 — 3 July 2020 COMPANY PUBLIC 544533 101 / 133 8.3.1.1.6 Disable I2C Interface NTAG 5 link offers the option to disable the I2C interface temporarily using the session register bit DISABLE_I2C (see Table 100). With this feature, the NFC Device can easily get exclusive access to EEPROM. This feature can be enabled via the NFC interface during the session by setting related session bit. 8.3.1.2 Master mode of NTP5332 NTAG 5 link can be configured in I2C master mode. Using I2C Master interface, I2C slave device like sensors or memories can be connected to NTAG 5 link without an external microcontroller. Using energy harvesting capability, I2C device can be powered by NTAG 5 link . When using I2C master mode, it must be ensured, that there is no other active I2C master on the same bus. The USE_CASE_CONF needs to be set to I2C master (01b) and SRAM needs to be enabled in CONFIG_1 byte (see Table 38). The used clock speed can be configured by setting I2C_MASTER_SCL_LOW and I2C_MASTER_SCL_HIGH (see Section 8.1.3.21). To communicate with the connected I2C slave device two custom commands are implemented. • WRITE I2C (see Section 8.2.3.8.1) • READ I2C (see Section 8.2.3.8.2) The response from the READ I2C command will be stored in the SRAM and can be read (see Section 8.2.3.6.1) afterwards from NFC perspective. Due to the 256 byte SRAM, only 256 bytes can be written / read at once to / from the I2C interface. Of course, all other NFC commands are working in master mode and the user memory as well as configuration memory is accessible from NFC perspective. WARNING: When enabling I2C master mode and disabling NFC interface in parallel, NTAG 5 link gets disabled for current session. Implementation details can be found in AN12368. 8.3.1.3 Watch Dog Timer A programmable watchdog timer is implemented to unlock the I2C host from NTAG 5 link latest after a defined maximum time period. The host itself will not be notified of this event directly but the NFC status register is updated accordingly. On default Watch Dog Timer is enabled with a value of 0848h (~20 ms) but the watchdog timer can be freely set with WDT_CONFIG from 0000h (9.434 μs) up to (FFFFh+1) * 9.434 µs (~618 ms). It is recommended to keep this time as short as possible, by setting the value above, but close to the maximum needed I2C transaction time. The timer is only active, when WDT_ENABLE is set to 1b and the IC is VCC powered. The timer starts ticking when the I2C communication starts. The Watch Dog Timer ensures, that I2C interface gets released after the configured time period in any case. In the case where the I2C communication has completed before the end of the timer and the status register I2C_IF_LOCKED was not cleared by the host, it will be cleared when defined watchdog time elapses. |
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