NTP53X2 datasheet(106/133 Pages) NXP

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NXP Semiconductors

NTP53x2

NTAG 5 link - NFC Forum-compliant I2C bridge

NTP53x2

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Product data sheet

Rev. 3.3 — 3 July 2020

COMPANY PUBLIC

544533

106 / 133

8.4 Arbitration between NFC and I2C interface

There are different modes implement to ensure access to the EEPROM and described in

detail hereafter. Two status bits (I2C_IF_LOCKED and NFC_IF_LOCKED) are provided

to show the status of arbiter.

Details about the different arbitrations modes can be found in AN12364.

8.4.1 NFC Mode

If NTAG 5 link is only powered by NFC, arbiter needs only to lock to the NFC interface

if the IC receives a valid NFC command. After completion of the NFC command,

NFC_IF_LOCKED will be cleared automatically.

8.4.2 I2C Mode

If NTAG 5 link is only powered by VCC, arbiter needs only to lock to the I2C interface

if the IC is correctly addressed for the memory access. The host needs to clear

I2C_IF_LOCKED. Otherwise, the bit will be cleared automatically if the watchdog timer

expires.

In I2C mode, availability of the SRAM as part of the memory depends on

SRAM_ENABLE bit.

8.4.3 Normal Mode

If NTAG 5 link is powered by NFC and VCC, arbiter locks interface on a first come first

serve principle.

When receiving a valid NFC command and access is not locked to I2C, then the arbiter

locks to the NFC interface. After completion of the NFC command, the lock will be

released automatically. The host can access the registers at any time. Only access to

EEPROM is locked.

When NTAG 5 link is correctly addressed by its I2C address for the memory access and

access is not locked to NFC, then the arbiter locks to the I2C interface. The host needs

to clear the lock actively. If not, the lock will be released automatically as soon as the

watchdog timer expires. NFC reader can access the registers at any time. Only access to

EEPROM is locked.

In this mode, availability of the SRAM depends on SRAM_ENABLE bit.

How to exchange data based on NDEF messages is defined in NFC Forum Tag NDEF

Exchange Protocol (TNEP) Specification.

8.4.4 SRAM Mirror Mode

In this mode arbiter works like in normal mode with the exception, that SRAM is used

instead of EEPROM.

8.4.5 SRAM Pass-Through Mode

In this mode, the NTAG 5 link transfers data from NFC to I2C and vice versa using the

SRAM. The arbiter switches automatically between the two interfaces when accessing

the terminator block (last block of SRAM).

Details can be found in AN12364.

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