WatchDog Timer
28
PRELIMINARY V1.8
TABLE 21.
The Description of WDCR bit-7 to 4
TABLE 22.
The Description of WDCR bit-3 to 0
10.3.
WatchDog Timer Register (WDCNT)
WDREN[1:0]
5 to 4
WD-Timer Reset generation ENable bits
[Bit Status: 01 (Initial Value)]
In this mode, the WD-Timer can not generate a Reset signal even though the
underflow of the WD-Timer takes place. This allows the WD-Timer to be used as
a simple Interval Timer.
[Bit Status: 10]
In this mode, the WD-Timer will generate a Reset signal if the underflow of the
WD-Timer takes place. After WD-Timer Reset, the program will begin at the
ROM address 0000H. All registers will be initialized.
[Bit Status: 00 or 11]
Do NOT write these values on these two bits.
In these mode, the WD-Timer will generate a Reset signal just like status-10 if
the underflow of the WD-Timer takes place. The purpose of these two redundant
status is to prevent unexpected WD-Timer behavior by device upset. While the
WD-Timer is running with setting 10 to the WDREN[1:0], unexpected electrical
shock can make a WDREN bit toggle. If another WDREN bit retain its value, the
WD-Timer can generate a Reset signal.
Name
Bit
Description
WDRST
3
WD-Timer Reset Status bit
[Bit Status: 0]
The chip was initialized by the external pin reset signal.
[Bit Status: 1]
The chip was initialized by the WD-Timer underflow reset signal.
2
Reserved bit
WDCS[1:0]
1 to 0
WD-Timer counting Clock Select bit
[Bit Status: 00]
Fsys/12
[Bit Status: 01]
Ffast/2
5 = F
fast/32
[Bit Status: 10]
Ffast/2
10 = F
fast/1024
[Bit Status: 11]
Ffast/2
14 = F
fast/16384
Address
Bit Addr.
None
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