80 / 129 page  Port Definitions PRELIMINARY V1.8 75 TABLE 46. Definition of P2 TABLE 47. Definition of P2IO Write by Hardware Address CAH Bit Addr. None BIT 7 6 5 4 3 2 1 0 NAME P2IO7 P2IO6 P2IO5 P2IO4 P2IO3 P2IO2 P2IO1 P2IO0 Definition Port-2 I/O Control Register bit-7 0: Input Mode 1: Output Mode Port-2 I/O Control Register bit-6 0: Input Mode 1: Output Mode Port-2 I/O Control Register bit-5 0: Input Mode 1: Output Mode Port-2 I/O Control Register bit-4 0: Input Mode 1: Output Mode Port-2 I/O Control Register bit-3 0: Input Mode 1: Output Mode Port-2 I/O Control Register bit-2 0: Input Mode 1: Output Mode Port-2 I/O Control Register bit-1 0: Input Mode 1: Output Mode Port-2 I/O Control Register bit-0 0: Input Mode 1: Output Mode Reset Value 0 0 0 0 0 0 0 0 Read/Write by Software R/W R/W R/W R/W R/W R/W R/W R/W Write by Hardware Address CBH Bit Addr. None BIT 7 6 5 4 3 2 1 0 NAME P2RD7 P2RD6 P2RD5 P2RD4 P2RD3 P2RD2 P2RD1 P2RD0 Definition Port-2 Resistor Disable Register bit-7 0: Resistor Enable 1: Disable Port-2 Resistor Disable Register bit-6 0: Resistor Enable 1: Disable Port-2 Resistor Disable Register bit-5 0: Resistor Enable 1: Disable Port-2 Resistor Disable Register bit-4 0: Resistor Enable 1: Disable Port-2 Resistor Disable Register bit-3 0: Resistor Enable 1: Disable Port-2 Resistor Disable Register bit-2 0: Resistor Enable 1: Disable Port-2 Resistor Disable Register bit-1 0: Resistor Enable 1: Disable Port-2 Resistor Disable Register bit-0 0: Resistor Enable 1: Disable |
|
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
