76 / 129 page  Port Definitions PRELIMINARY V1.8 71 TABLE 42. Definition of P0 Address 80H Bit Addr. 87H 86H 85H 84H 83H 82H 81H 80H BIT 7 6 5 4 3 2 1 0 NAME P07 P06 P05 P04 P03 P02 P01 P00 Definition Port-0 Pin or Latch bit-7 Port-0 Pin or Latch bit-6 Port-0 Pin or Latch bit-5 Port-0 Pin or Latch bit-4 Port-0 Pin or Latch bit-3 Port-0 Pin or Latch bit-2 Port-0 Pin or Latch bit-1 Port-0 Pin or Latch bit-0 Reset Value 1 1 1 1 1 1 1 1 Read/Write by Software R/W RMW Ins: P07 Latch Read Other Ins: P0.7 Pin Read R/W RMW Ins: P06 Latch Read Other Ins: P0.6 Pin Read R/W RMW Ins: P05 Latch Read Other Ins: P0.5 Pin Read R/W RMW Ins: P04 Latch Read Other Ins: P0.4 Pin Read R/W RMW Ins: P03 Latch Read Other Ins: P0.3 Pin Read R/W RMW Ins: P02 Latch Read Other Ins: P0.2 Pin Read R/W RMW Ins: P01 Latch Read Other Ins: P0.1 Pin Read R/W RMW Ins: P00 Latch Read Other Ins: P0.0 Pin Read Write by Hardware Address AAH Bit Addr. None BIT 7 6 5 4 3 2 1 0 NAME P0IO7 P0IO6 P0IO5 P0IO4 P0IO3 P0IO2 P0IO1 P0IO0 Definition Port-0 I/O Control Register bit-7 0: Input Mode 1: Output Mode Port-0 I/O Control Register bit-6 0: Input Mode 1: Output Mode Port-0 I/O Control Register bit-5 0: Input Mode 1: Output Mode Port-0 I/O Control Register bit-4 0: Input Mode 1: Output Mode Port-0 I/O Control Register bit-3 0: Input Mode 1: Output Mode Port-0 I/O Control Register bit-2 0: Input Mode 1: Output Mode Port-0 I/O Control Register bit-1 0: Input Mode 1: Output Mode Port-0 I/O Control Register bit-0 0: Input Mode 1: Output Mode Reset Value 0 0 0 0 0 0 0 0 Read/Write by Software R/W R/W R/W R/W R/W R/W R/W R/W Write by Hardware |
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