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Power-Saving Modes
62
PRELIMINARY V1.8
TABLE 33.
Device States in Power-Saving Modes
13.10. Power-Saving Control Register (PSCR)
Block
FastAll
SlowAll
StopAll
FastPeri
SlowPeri
Fast Oscillator
Run
Stop
Stop
Run
Stop
Slow Oscillator
Run
Run
Stop
Run
Run
System Clock
from
Fast OSC
from
Slow OSC
Stop
from
Fast OSC
from
Slow OSC
CPU Clock
from
Fast OSC
from
Slow OSC
Stop
Stop
Stop
Peripheral Clock
from
Fast OSC
from
Slow OSC
Stop
from
Fast OSC
from
Slow OSC
Instruction
Run(fast)
Run(slow)
Stop
Stop
Stop
CPU SFR
Run(fast)
Run(slow)
Retained
Retained
Retained
RAM
Run(fast)
Run(slow)
Retained
Retained
Retained
Peripheral
Run(fast)
Run(slow)
Stop
Run(fast)
Run(slow)
Peri SFR
Run(fast)
Run(slow)
Retained
Run(fast)
Run(slow)
Address
97H
Bit Addr.
None
BIT
7
6
5
4
3
2
1
0
NAME
FTST
HIZ
NOTS
SSTP
FSTP
ISTP
Definition
Fast Sta-
bilization
Time for
Test
High
Imped-
ance
Not Use
Slow
Clock
Slow clock
SToP
Fast clock
SToP
CPU clock
SToP
Reset
Value
0
0
0
0
0
0
Read/
Write by
Software
R/W
R/W
R/W
R/W
R/W
R/W
Write by
Hardware
0 by
An IRQ1
Event
0 by
An IRQ1
Event
0 by
Interrupt
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