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SS1102C Datasheet(PDF) 75 Page - List of Unclassifed Manufacturers

Part # SS1102C
Description  Integrated MCU with Spread-Spectrum Transceiver (SST)
PDF  129 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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SS1102C Datasheet(HTML) 75 Page - List of Unclassifed Manufacturers

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Port Definitions
70
PRELIMINARY V1.8
is high, Port-0.x pull-up resistor is disconnected. If low, Port-0.x pull-up resistor is
connected. Initial status of P0RD is 00000000B, thus pull-up resistor is connected. If
ZCR0 (High-Z Control Register Bit-0) is high, High-Z control is enabled. At this time,
if HIZ bit in the PSCR (Power Saving Control Register) becomes high, pull-up resistor
is disconnected and pin status becomes high impedance.
To use Pin-0.0 to 0.7 as a normal output port, PCR0 should be high. If the P0IO bit-x is
high, Port-0.x is output mode. In output mode, pull-up resistor is not automatically
disconnected regardless P0RD bit-x. If ZCR0 (High-Z Control Register Bit-0) is high,
High-Z control is enabled. At this time, if HIZ bit in the PSCR (Power Saving Control
Register) becomes high, pin status becomes high impedance.
To use Pin-0.0 to 0.7 as an A/D input/output port, PCR0 should be low (reset value). If
PCR0 is low, the direction of each Port-0 pin is controlled by CPU. In input mode, pull-
up resistor can be connected by P0RD (Port-0 Resistor Disable Register). In output
mode, pull-up resistor is not automatically disconnected regardless P0RD bit-x. For the
A/D Mode, the ZCR0 must be low (reset value) not to support Hi-Z state.
When P0NOPNx = 0, Port-0.x output buffer will be CMOS Push-Pull. But, P0NOPNx
= 1, Port-0.x output buffer will become N-channel Open Drain.
Figure 25.
PORT-0
MUX
0
1
SFR
P0
[7:0]
Pin
SFR
P0RD
[7:0]
To
CPU
MUX
Read-Modify-Write
ADDR/DATA
R
PMOS
VDD
or
Output Enable
NHIZ



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