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Power-Saving Modes
64
PRELIMINARY V1.8
TABLE 35.
The Definition of Each PSCR bit
13.11. Stop Release Register (SREL)
TABLE 36.
Summary of SREL
SSTP
2
Slow clock SToP bit
[Bit Status: 0] Slow oscillator (32.768KHz) operates.
[Bit Status: 1] Slow oscillator stops.
FSTP
1
Fast clock SToP bit
[Bit Status: 0]
Fast oscillator (up to 24MHz) operates and drives all CPU and peripherals.
[Bit Status: 1]
Fast oscillator stops. Slow oscillator (32.768KHz) may or may not drive all
CPU and peripherals.
ISTP
0
Instruction SToP bit
[Bit Status: 0]
CPU control clocks drive CPU.
Thus, instructions may be executed its operations normally.
[Bit Status: 1]
CPU control clocks stop.
Thus, CPU stops to execute instructions.
Address
96H
Bit Addr.
None
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SREL1
SREL0
Definition
Stop Release
bit-1
Stop
Release bit-
0
Reset Value
0
0
0
0
0
0
0
0
Read/Write
by Software
R
R
R
R
R
R
R/W
R/W
Write
by Hardware
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