68 / 129 page
Power-Saving Modes
PRELIMINARY V1.8
63
TABLE 34.
Summary of PSCR
Figure 22.
Clock System & Power-saving Control
Name
Bit
Definition
FSEL[1:0]
7 to 6
Reserved
FTST
5
Fast Stabilization Time for Test
[Bit Status: 0]
When the StopAll mode is released by an IRQ1 Event, fast oscillator stabiliza-
tion time will be 19.4688 mSec (1/10MHz x (218-1+217-1)).
[Bit Status: 1]
When the StopAll mode is released by an IRQ1 Event, fast oscillator stabiliza-
tion time will be 6.4 uSec (1/10MHz x 27-1).
HIZ
4
PIN State control bit
[Bit Status: 0] Normal Pin state.
[Bit Status: 1] All normal I/O pins become High-Z (impedance) state.
NOTS
3
Not Use Slow Oscillator bit
[Bit Status: 0] Slow oscillator (32.768KHz) is used.
[Bit Status: 1]
Slow oscillator is not used. The pin XSIN is connected to ground.
Fast Clock
Generator
Slow Clock
Generator
(32.768K)
FSTP
SSTP
Mux &
Sync
CPU
Clock
Peripheral
ISTP
Generator
Generator
Clock
System
Clock
CPU
Control
Clocks
Peripheral
Control
Clocks
Peripheral Blocks
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
