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SS1102C Datasheet(PDF) 48 Page - List of Unclassifed Manufacturers

Part # SS1102C
Description  Integrated MCU with Spread-Spectrum Transceiver (SST)
PDF  129 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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SS1102C Datasheet(HTML) 48 Page - List of Unclassifed Manufacturers

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Direct Sequence Spread Spectrum Baseband Modem (SSTM)
PRELIMINARY V1.8
43
up a burst at the end of transmission of the user’s data, “1”s will be sent automatically
(when there is no data and transmission is enabled, all “1”s will be sent).
When RXFIFO interrupt indicates that the RXshh bit is initiated, data bytes should be
read from the RXFIFO. The high level protocol should take care of the end of
transmission to avoid situation when some data can be held in the RXFIFO indefinitely
or lost on the Reset. Status bits for the overflow and underflow for the TXFIFO and
overflow for the RXFIFO are provided.
The timing relationship between the data and interrupt signals for transmit and receive
is shown in Figure 16. below. The rate with which the MCU feeds data to the transmitter
depends on the values of thresholds and burst rates.
A typical start-up of the data link is also shown in Figure 17.
In the full-duplex mode the SSTM when programmed as a Master, starts transmission as
soon as reset is released (RTS_N is enabled). As long as the Master is powered-on, the
SSTM will send out the acquisition burst and try to establish a communication link with
a remote Slave. Thus, the communication channel is occupied as soon as the Master
resets, and this can occur before any data becomes available for transmission. Once the
communication link is established, even when there is no data to be transmitted, the
Master and Slave will remain in communication with each other (sending out “1” in the
data field) indefinitely or until the Master is disabled.
Figure 16.
Full-Duplex Data Interface Timing
12.9.2
Threshold Value Calculation
The performance of the MCU should be considered when calculating TXshl and RXshh.
The time for transmission of the TXshl bytes out of the TX FIFO should be more than
the time required by the MCU to write new data into the TX FIFO. Accordingly, the
IS[2]
IS[3]
Data
READ
WRITE



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