Port Definitions
PRELIMINARY V1.8
77
is high, Port-1.x pull-up resistor is disconnected. If low, Port-1.x pull-up resistor is
connected. Initial status of P1RD is 00000000B, thus pull-up resistor is connected. If
ZCR1 (High-Z Control Register Bit-1) is high, High-Z control is enabled. At this time,
if HIZ bit in the PSCR (Power Saving Control Register) becomes high, pull-up resistor
is disconnected and pin status becomes high impedance. In input mode, P1.4/LBD,
P1.6/SPIIN, and P1.7/SPICLK can be used LBD or SPI input pins.
To use Pin-1.0 to 1.7 as a normal output port, PCR1 should be high. If the P1IO bit-x is
high, Port-1.x is output mode. In output mode, pull-up resistor is not automatically
disconnected regardless P1RD bit-x. If ZCR1 (High-Z Control Register Bit-1) is high,
High-Z control is enabled. At this time, if HIZ bit in the PSCR (Power Saving Control
Register) becomes high, pin status becomes high impedance.
To use P1.5/SPIO and P1.7/SPICLK as an SPIO output port, PCR1 should be high.
And, an SPI output should be enabled in the SPI block.
When P1NOPNx = 0, Port-1.x output buffer will be CMOS Push-Pull. But, P1NOPNx
= 1, Port-1.x output buffer will become N-channel Open Drain.
TABLE 50.
Definition of P1
Address
90H
Bit Addr.
97H
96H
95H
94H
93H
92H
91H
90H
BIT
7
6
5
4
3
2
1
0
NAME
P17
P16
P15
P14
P13
P12
P11
P10
Definition
Port-1 Pin
or Latch
bit-7
Port-1 Pin
or Latch
bit-6
Port-1 Pin
or Latch
bit-5
Port-1 Pin
or Latch
bit-4
Port-1 Pin
or Latch
bit-3
Port-1 Pin
or Latch
bit-2
Port-1 Pin
or Latch
bit-1
Port-1 Pin
or Latch
bit-0
Reset Value
1
1
1
1
1
1
1
1
Read/Write
by Software
R/W
RMW Ins:
P17 Latch
Read
Other Ins:
P1.7 Pin
Read
R/W
RMW Ins:
P16 Latch
Read
Other Ins:
P1.6 Pin
Read
R/W
RMW Ins:
P15 Latch
Read
Other Ins:
P1.5 Pin
Read
R/W
RMW Ins:
P14 Latch
Read
Other Ins:
P1.4 Pin
Read
R/W
RMW Ins:
P13 Latch
Read
Other Ins:
P1.3 Pin
Read
R/W
RMW Ins:
P12 Latch
Read
Other Ins:
P1.2 Pin
Read
R/W
RMW Ins:
P11 Latch
Read
Other Ins:
P1.1 Pin
Read
R/W
RMW Ins:
P10 Latch
Read
Other Ins:
P1.0 Pin
Read
Write
by Hardware
Address
BAH
Bit Addr.
None
BIT
7
6
5
4
3
2
1
0
NAME
P1IO7
P1IO6
P1IO5
P1IO4
P1IO3
P1IO2
P1IO1
P1IO0
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