 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
Z8F082ASH020SC Datasheet(PDF) 66 Page - Zilog, Inc. |
|
|
|||||||||||||||||||||||||||||
Z8F082ASH020SC Datasheet(HTML) 66 Page - Zilog, Inc. |
|
|
66 / 244 page  PS024705-0405 P R E L I M I N A R Y Interrupt Controller Z8 Encore! XP® F08xA Series Product Specification 48 Architecture Figure 7 illustrates the interrupt controller block diagram. Figure 7.Interrupt Controller Block Diagram Operation Master Interrupt Enable The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions: • Execution of an EI (Enable Interrupt) instruction • Execution of an IRET (Return from Interrupt) instruction Lowest 0036H Port C0, both input edges 0038H Reserved Table 31. Trap and Interrupt Vectors in Order of Priority (Continued) Priority Program Memory Vector Address Interrupt or Trap Source Vector IRQ Request High Priority Medium Priority Low Priority Priority Mux Port Interrupts Internal Interrupts |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
