Z8F082ASH020SC datasheet(90/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Timers

Z8 Encore! XP® F08xA Series

Product Specification

Timer Control Register Definitions

Timer 0–1 High and Low Byte Registers

The Timer 0–1 High and Low Byte (TxH and TxL) registers (Tables 47 and 49) contain

the current 16-bit timer count value. When the timer is enabled, a read from TxH causes

the value in TxL to be stored in a temporary holding register. A read from TxL always

returns this temporary register when the timers are enabled. When the timer is disabled,

reads from the TxL reads the register directly.

Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-

mended. There are no temporary holding registers available for write operations, so simul-

taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are

written during counting, the 8-bit written value is placed in the counter (High or Low

Byte) at the next clock edge. The counter continues counting from the new value.

TH and TL—Timer High and Low Bytes

These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.

Timer Reload High and Low Byte Registers

The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) registers (Tables 49 and 51)

store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload

High Byte register are stored in a temporary holding register. When a write to the Timer

Reload Low Byte register occurs, the temporary holding register value is written to the

Timer High Byte register. This operation allows simultaneous updates of the 16-bit Timer

Table 47. Timer 0–1 High Byte Register (TxH)

BITS

FIELD

RESET

000

R/W

R/WR/W

ADDR

F00H, F08H

Table 48. Timer 0–1 Low Byte Register (TxL)

BITS

FIELD

RESET

000

R/W

R/WR/W

ADDR

F01H, F09H

Z8F082ASH020SC Datasheet(PDF) 90 Page - Zilog, Inc.

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