Z8F082ASH020SC datasheet(100/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Watch-Dog Timer

Z8 Encore! XP® F08xA Series

Product Specification

All three Watch-Dog Timer Reload registers must be written in the order just listed. There

must be no other register writes between each of these operations. If a register write

occurs, the lock state machine resets and no further writes can occur unless the sequence is

restarted. The value in the Watch-Dog Timer Reload registers is loaded into the counter

when the Watch-Dog Timer is first enabled and every time a WDT instruction is executed.

Watch-Dog Timer Control Register Definitions

Watch-Dog Timer Control Register

The Watch-Dog Timer Control (WDTCTL) register is a write-only control register. Writ-

ing the 55H, AAH unlock sequence to the WDTCTL register address unlocks the three

Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes

to the time-out period. These write operations to the WDTCTL register address produce

no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious

writes to the Reload registers.

This register address is shared with the read-only Reset Status Register.

WDTUNLK—Watch-Dog Timer Unlock

The user software must write the correct unlocking sequence to this register before it is

allowed to modify the contents of the watch-dog timer reload registers.

Watch-Dog Timer Reload Upper, High and Low Byte Registers

The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) reg-

isters (Tables 57 through 59) form the 24-bit reload value that is loaded into the Watch-

Dog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0],

WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the appropriate Reload Value.

Reading from these registers returns the current Watch-Dog Timer count value.

Table 56. Watch-Dog Timer Control Register (WDTCTL)

BITS

FIELD

WDTUNLK

RESET

XXX

R/W

WWW

ADDR

FF0H

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