Z8F082ASH020SC datasheet(67/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Interrupt Controller

Z8 Encore! XP® F08xA Series

Product Specification

• Writing a 1 to the IRQE bit in the Interrupt Control register

Interrupts are globally disabled by any of the following actions:

• Execution of a DI (Disable Interrupt) instruction

• eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller

• Writing a 0 to the IRQE bit in the Interrupt Control register

• Reset

• Execution of a Trap instruction

• Illegal Instruction Trap

• Primary Oscillator Fail Trap

• Watch-Dog Oscillator Fail Trap

Interrupt Vectors and Priority

The interrupt controller supports three levels of interrupt priority. Level 3 is the highest

priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of

the interrupts are enabled with identical interrupt priority (all as Level 2 interrupts, for

example), the interrupt priority is assigned from highest to lowest as specified in Table 31

on page 47. Level 3 interrupts are always assigned higher priority than Level 2 interrupts

which, in turn, always are assigned higher priority than Level 1 interrupts. Within each

interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in

Table 31, above. Reset, Watch-Dog Timer interrupt (if enabled), Primary Oscillator Fail

Trap, Watchdog Oscillator Fail Trap, and Illegal Instruction Trap always have highest

(level 3) priority.

Interrupt Assertion

Interrupt sources assert their interrupt requests for only a single system clock period (sin-

gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-

ing bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a

0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt

request.

The following coding style that clears bits in the Interrupt Request registers is NOT rec-

ommended. All incoming interrupts received between execution of the first LDX com-

mand and the final LDX command are lost.

Poor coding style that can result in lost interrupt requests:

LDX r0, IRQ0

AND r0, MASK

LDX IRQ0, r0

Caution:

Z8F082ASH020SC Datasheet(PDF) 67 Page - Zilog, Inc.