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Z8F082ASH020SC Datasheet(PDF) 60 Page - Zilog, Inc.

Part # Z8F082ASH020SC
Description  Z8 Encore XP-R F08xA Series with eXtended Peripherals
PDF  244 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8F082ASH020SC Datasheet(HTML) 60 Page - Zilog, Inc.

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PS024705-0405
P R E L I M I N A R Y
General-Purpose I/O
Z8 Encore! XP® F08xA Series
Product Specification
42
PPUE[7:0]—Port Pull-up Enabled
0 = The weak pull-up on the Port pin is disabled.
1 = The weak pull-up on the Port pin is enabled.
Port A–D Alternate Function Set 1 Sub-Registers
The Port A–D Alternate Function Set1 sub-register (Table 24) is accessed through the Port
A–D Control register by writing 07H to the Port A–D Address register. The Alternate
Function Set 1 sub-registers selects the alternate function available at a port pin. Alternate
Functions selected by setting or clearing bits of this register are defined in “GPIO Alternate
Functions” on page 32
.
Alternate function selection on port pins must also be enabled as decribed in “Port A–D
Alternate Function Sub-Registers” on page 39.
PAFS1[7:0]—Port Alternate Function Set 1
0 = Port Alternate Function selected as defined in Table 13 in the GPIO Alternate Functions
section.
1 = Port Alternate Function selected as defined in Table 13 in the GPIO Alternate Functions
section.
Port A–D Alternate Function Set 2 Sub-Registers
The Port A–D Alternate Function Set 2 sub-register (Table 25) is accessed through the
Port A–D Control register by writing 08H to the Port A–D Address register. The Alternate
Function Set 2 sub-registers selects the alternate function available at a port pin. Alternate
Functions selected by setting or clearing bits of this register is defined in Table 13 in the
section “GPIO Alternate Functions” on page 32.
Alternate function selection on port pins must also be enabled as decribed in “Port A–D
Alternate Function Sub-Registers” on page 39.
Table 24. Port A–D Alternate Function Set 1 Sub-Registers (PxAFS1)
BITS
7
6
5
4
3
2
1
0
FIELD
PAFS17
PAFS16
PAFS15
PAFS14
PAFS13
PAFS12
PAFS11
PAFS10
RESET
0
000
00
00
R/W
R/WR/W
R/WR/W
R/WR/W
R/WR/W
ADDR
If 07H in Port A–D Address Register, accessible through the Port A–D Control Register
Table 25. Port A–D Alternate Function Set 2 Sub-Registers (PxAFS2)
BITS
7
6
5
4
3
2
1
0
FIELD
PAFS27
PAFS26
PAFS25
PAFS24
PAFS23
PAFS22
PAFS21
PAFS20
Note:
Note:



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