Z8F082ASH020SC datasheet(81/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Timers

Z8 Encore! XP® F08xA Series

Product Specification

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Select either the rising edge or falling edge of the comparator output signal for the

count. This also sets the initial logic level (High or Low) for the Timer Output

alternate function. However, the Timer Output function is not required to be

enabled.

2. Write to the Timer High and Low Byte registers to set the starting count value. This

action only affects the first pass in COMPARATOR COUNTER mode. After the first

timer Reload in COMPARATOR COUNTER mode, counting always begins at the

reset value of 0001H. Generally, in COMPARATOR COUNTER mode the Timer

High and Low Byte registers must be written with the value 0001H.

3. Write to the Timer Reload High and Low Byte registers to set the Reload value.

4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing

to the relevant interrupt registers.

5. If using the Timer Output function, configure the associated GPIO port pin for the

Timer Output alternate function.

6. Write to the Timer Control register to enable the timer.

In COMPARATOR COUNTER mode, the number of comparator output transitions since

the timer start is given by the following equation:

PWM SINGLE OUTPUT Mode

In PWM SINGLE OUTPUT mode, the timer outputs a Pulse-Width Modulator (PWM)

output signal through a GPIO Port pin. The timer input is the system clock. The timer first

counts up to the 16-bit PWM match value stored in the Timer PWM High and Low Byte

registers. When the timer count value matches the PWM value, the Timer Output toggles.

The timer continues counting until it reaches the Reload value stored in the Timer Reload

High and Low Byte registers. Upon reaching the Reload value, the timer generates an

interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and

counting resumes.

If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as

a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The

Timer Output signal returns to a High (1) after the timer reaches the Reload value and is

reset to 0001H.

If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as

a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The

Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is

reset to 0001H.

The steps for configuring a timer for PWM Single Output mode and initiating the PWM

operation are as follows:

Comparator Output Transitions

Current Count Value

Start Value

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Z8F082ASH020SC Datasheet(PDF) 81 Page - Zilog, Inc.

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