PC8374L datasheet(116/239 Pages) NSC

116 / 239 page

6.0 General-Purpose Input/Output (GPIO) Ports (Continued)

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116

Revision1.1

6.4.3

GPIO Data Out Register (GPDO)

Power Well: VSB3

Location:

Device specific

Type:

R/W or RO

6.4.4

GPIO Data In Register (GPDI)

Power Well: VSB3

Location:

Device specific

Type:

6.4.5

GPIO Event Enable Register (GPEVEN)

Power Well: VSB3

Location:

Device specific

Type:

R/W or RO

Bit

76543210

Name

DATAOUT

Reset

11111111

Bit

Description

7-0

DATAOUT (Data Out). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. The value of each bit determines the

value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the

written data unless the bit is locked by the GPCFG register Lock bit. Reading the bit returns its value regardless

of the pin value and conﬁguration.

0: Corresponding pin driven to low

1: Corresponding pin driven or released (according to buffer type selection) to high (default)

Bit

76543210

Name

DATAIN

Reset

XXXXXXXX

Bit

Description

7-0

DATAIN (Data In). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. Reading each bit returns the value of the

corresponding GPIO pin. Pin conﬁguration and the GPDO register value may inﬂuence the pin value. Write is

ignored.

0: Corresponding pin level low

1: Corresponding pin level high

Bit

76543210

Name

EVTENA

Reset

00000000

Bit

Description

7-0

EVTENA (Event Enable). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. Each bit enables system

notiﬁcation by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in GPEVST

0: Event pending by corresponding GPIO pin masked

1: Event pending by corresponding GPIO pin enabled

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PC8374L Datasheet(PDF) 116 Page - National Semiconductor (TI)

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