28HS01GTAM03 datasheet(109/138 Pages) INFINEON

109 / 138 page

Datasheet

109 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Timing characteristics

Table 85

Timing characteristics[45]

Symbol

Parameter

Min

Typ

Max

Unit

Reference

figure

Octal SDR/DDR

fCK

CK Clock Frequency for Octal mode transactions using DS

(HS-T)



200

MHz



CK Clock Frequency for Octal mode transactions using DS

(HL-T)



166

pCK

CK Clock Period

1/fCK



∞

Figure 72

tCH

Clock High Time

45% pCK



55% pCK

Figure 75

tCL

Clock Low Time



tCS

CS# High Time (Read transactions)



Figure 78 /

Figure 79

CS# High Time Between Transactions (Interface CRC Read



CS# High Time (Program / Erase transactions)



tCSS

CS# Active Setup Time (relative to CK)



tCSH0

CS# Active Hold Time (relative to CK in Mode 0)



tCSH3

CS# Active Hold Time (relative to CK in Mode 3)

6.5



tSU

HS-T Data Setup Time (all VCC)

0.5



HL-T Data Setup Time (all VCC)0.6



tHD

HL-T Data Hold Time (all VCC)0.6



HS-T Data Hold Time (all VCC)0.5



tV[43]

Clock Low to Output Valid (15pF Loading) (HS-T)



5.45

Figure 78 /

Figure 80

Clock Low to Output Valid (15pF Loading) (HL-T)



7.25

tCKDS

DS Valid (HS-T)



5.45

DS Valid (HL-T)



7.25

tDSS[51] DS transition to Data Valid

0.4



0.4

tDSH[51] DS transition to Data Invalid

0.4



0.4

tHO

Output Hold Time

0.4



Figure 78

tDIS[44]

CS# Inactive to Output Disable Time (HS-T) (SDR / DDR)



6.50 / 6.0

Figure 78 /

Figure 80

CS# Inactive to Output Disable Time (HL-T)



7.50

tDSZ

CS# Inactive to DS Disable Time (HS-T) (SDR / DDR)



6.50 / 6.0

CS# Inactive to DS Disable Time (HL-T)



7.50

tIO_SKEW[5

Data Skew (First Data Bit to Last Data Bit)



0.5



tPS

Program/Erase Transaction CS# Invalid to Program Suspend /

Erase Suspend Transaction CS# Invalid (Interface CRC)



µs

Figure 41

tCSDS

CS# Low to DS Low



Figure 30 /

Figure 31

SPI SDR

fCK

CK Clock Frequency



166

MHz



pCK

CK Clock Period

1/ fCK



∞

Figure 72

Notes

43. Full VCC range and CL = 15pF.

44. Output HI-Z is defined as the point where data is no longer driven.

45. Applicable across all operating temperature options.

46. If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine when CS# may go Low.

47. Sum of tRP and tRH must be equal to or greater than tRPH.

48. Typical program and erase times assume the following conditions: 25°C, VCC = 1.8V and 3.0V; checkerboard data pattern.

49. The programming time for any OTP programming transaction is the same as tPP. This includes PRSSR_4_1.

50. The programming time for the PRPPB_4_0 transaction is the same as tPP. The erase time for ERPPB_0_0 transaction is the same as tSE.

51. Values are guaranteed by characterization and not 100% tested in production.

52. Guaranteed by design.

53. The Joint Electron Device Engineering Council (JEDEC) standard JESD22-A117 defines the procedural requirements for performing valid endurance

and retention tests based on a qualification specification. This methodology is intended to determine the ability of a flash device to sustain repeated

data changes without failure (program/erase endurance) and to retain data for the expected life (data retention). Endurance and retention qualifica-

tion specifications are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.

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