28HS01GTAM03 datasheet(110/138 Pages) INFINEON

110 / 138 page

Datasheet

110 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Timing characteristics

tCH

Clock High Time

45% pCK



55% pCK

Figure 75

tCL

Clock Low Time

45% pCK



55% pCK

tCS

CS# High Time (Read transactions)



Figure 76 /

Figure 77

CS# High Time Between Transactions (aborted commands)



CS# High Time (Program / Erase transactions)



tCSS

CS# Active Setup Time relative to CK (fCK  50MHz / fCK > 50MHz)

5/4



Figure 76

tCSH0

CS# Active Hold Time (relative to CK in Mode 0)



tCSH3

CS# Active Hold Time (relative to CK in Mode 3)



tSU

Data Setup Time (all VCC) (fCK  50MHz / fCK > 50MHz)

5 / 2



tHD

Data Hold Time (all VCC) (fCK  50MHz / fCK > 50MHz)

5 / 2



Clock Low to Output Valid

(15pF Loading, 3.0V  3.6V, 30  Output Impedance) (HL-T)



6.5

Figure 77

Clock Low to Output Valid (30pF Loading) (HS-T)



Clock Low to Output Valid (30pF Loading) (HL-T)



Clock Low to Output Valid (15pF Loading) (HS-T)



Clock Low to Output Valid (15pF Loading) (HL-T)



tHO

Output Hold Time

1.5



tDIS

Output Disable Time (HS-T)



Output Disable Time (HL-T)



7.50

Power Up / Power Down Timing

tPU

VCC(min) to Read operation

(HL256T / HS256T)

(HL512T / HS512T)

(HL01GT / HS01GT)

–



550 / 600

450 / 500

500 / 500

µs

Figure 63

tPD

VCC(Low) time



–

Figure 64

tVR[52]

VCC / VCCQ Power Up ramp rate



–µs/V

Figure 65

tVF

VCC / VCCQ Power Down ramp rate

30.0



–µs/V

Deep Power Down Mode Timing

tENTDPD[52

]

Time to Enter DPD mode



µs



tEXTDPD

Time to Exit DPD mode

(HL256T / HS256T)

(HL512T / HS512T)

(HL01GT / HS01GT)



520 / 570

380 / 430

430 / 430

Figure 62

tCSDPD

Chip Select Pulse Width to Exit DPD

0.02



Reset Timing[46, 47]

tRS

Reset Setup - RESET# High before CS# Low



Figure 55

tRH

Reset Pulse Hold - RESET# Low to CS# Low

(HL256T / HS256T)

(HL512T / HS512T)

(HL01GT / HS01GT)

550 / 600

450 / 500

500 / 500



µs

tRP

RESET# Pulse Width

200



Table 85

Timing characteristics[45] (Continued)

Symbol

Parameter

Min

Typ

Max

Unit

Reference

figure

Notes

43. Full VCC range and CL = 15pF.

44. Output HI-Z is defined as the point where data is no longer driven.

45. Applicable across all operating temperature options.

46. If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine when CS# may go Low.

47. Sum of tRP and tRH must be equal to or greater than tRPH.

48. Typical program and erase times assume the following conditions: 25°C, VCC = 1.8V and 3.0V; checkerboard data pattern.

49. The programming time for any OTP programming transaction is the same as tPP. This includes PRSSR_4_1.

50. The programming time for the PRPPB_4_0 transaction is the same as tPP. The erase time for ERPPB_0_0 transaction is the same as tSE.

51. Values are guaranteed by characterization and not 100% tested in production.

52. Guaranteed by design.

53. The Joint Electron Device Engineering Council (JEDEC) standard JESD22-A117 defines the procedural requirements for performing valid endurance

and retention tests based on a qualification specification. This methodology is intended to determine the ability of a flash device to sustain repeated

data changes without failure (program/erase endurance) and to retain data for the expected life (data retention). Endurance and retention qualifica-

tion specifications are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.

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