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CLRC663 Datasheet(PDF) 88 Page - NXP Semiconductors

Part # CLRC663
Description  High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
PDF  177 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CLRC663 Datasheet(HTML) 88 Page - NXP Semiconductors

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NXP Semiconductors
CLRC663
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Bit
7
6
5
4
3
2
1
0
Access
rights
-
r/w
-
r/w
Table 149. TxSym10BurstLen register (address 30h)...continued
Bit
Symbol
Description
7
RFU
-
6 to 4
Sym1BurstLen
Specifies the number of bits issued for symbol 1 burst. The 3 bits encodes a range from
8 to 256 bit:
00h - 8bit
01h - 16bit
02h - 32bit
03h - 48bit
04h - 64bit
05h - 96bit
06h - 128bit
07h - 256bit
3
RFU
-
2 to 0
Sym0BurstLen
Specifies the number of bits issued for symbol 0 burst. The 3 bits encodes a range from
8 to 256 bit:
00h - 8bit
01h - 16bit
02h - 32bit
03h - 48bit
04h - 64bit
05h - 96bit
06h - 128bit
07h - 256bit
Table 150. TxSym10BurstLen bits
9.10.4 TxWaitCtrl
Bit
7
6
5
4
3
2
1
0
Symbol
TxWaitStart
TxWaitEtu
TxWait High
TxStopBitLength
Access
rights
r/w
r/w
r/w
r/w
Table 151. TxWaitCtrl register (address 31h); reset value: C0h
Bit
Symbol
Description
7
TxWaitStart
If cleared, the TxWait time is starting at the End of the send data (TX).
If set, the TxWait time is starting at the End of the received data (RX).
6
TxWaitEtu
If cleared, the TxWait time is TxWait × 16/13.56 MHz.
If set, the TxWait time is TxWait × 0.5 / DBFreq (DBFreq is the frequency of the bit
stream as defined by TxDataCon).
Table 152. TXWaitCtrl bits
CLRC663
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 5.3 — 3 January 2024
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