CLRC663 datasheet(91/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Bit

Symbol

Description

RxMultiple

If set, RxMultiple is activated and the receiver will not terminate automatically (refer

Section 8.10.3.6.

If set to logic 1, at the end of a received data stream an error byte is

added to the FIFO. The error byte is a copy of the Error register.

RxEOFType

0: EOF as defined in the RxEOFSymbolReg is expected.

1: ISO/IEC14443B EOF is expected.

Note: Clearing this bit to 0 and clearing bit 0 and bit 1 in the RxEOFSymbolReg disables

the EOF check.

EGT_Check

If set to 1, the EGT is checked and if it is too long

a protocol error is set. (This is only valid for ISO/IEC14443 Type B).

EMD_Sup

Enables the EMD suppression according to ISO/IEC14443. If an error occurs within

the first three bytes, these three bytes are assumed to be EMD, ignored and the FIFO

is reset. A collision is treated as an error as well If a valid SOF was received, the

EMD_Sup is set and a frame of less than 3 bytes had been received. RX_IRQ is not set

in this EMD error cases. If RxForceCRCWrite is set, the FIFO should not be read out

before three bytes are written into.

2 to 0

Baudrate

Defines the baud rate of the receiving signal.

2h: 26 kBd

3h: 52 kBd

4h: 106 kBd

5h: 212 kBd

6h: 424 kBd

7h: 847 kBd

all remaining values are RFU

Table 160. RxCtrl bits...continued

9.12.3 RxWait

Selects internal receiver settings.

Bit

Symbol

RxWaitEtu

RxWait

Access

rights

r/w

Table 161. RxWait register (address 36h)

Bit

Symbol

Description

RXWaitEtu

If set to 0, the RxWait time is RxWait × 16/13.56 MHz.

If set to 1, the RxWait time is RxWait × (0.5/DBFreq).

6 to 0

RxWait

Defines the time after sending, where every input is ignored.

Table 162. RxWait bits

9.12.4 RxThreshold

Selects minimum threshold level for the bit decoder.

CLRC663

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Product data sheet

Rev. 5.3 — 3 January 2024

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