511820003 datasheet(31/52 Pages) OSRAM

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Mira130

Functional Description

Datasheet

• PUBLIC

DS000715

• v6-00 • 2023-Aug-09

│ 30

Figure 33:

MIPI Data Packet DI Structure

Other useful MIPI control registers can be found below.

Figure 34:

MIPI Control Registers

Function

Address

Default Value

Description

MIPI lane number

16’h3018

’h72

Bit[7:5]: MIPI lane number

3’h0: 1-lane mode

3’h1: 2-lane mode

3’h3: 4-lane mode

MIPI output data mode

16’h3031

’h0a

Bit[3:0]: MIPI bit mode

4’h8: Raw8 mode

4’hc: Raw12 mode

Others: Raw10 mode

PHY data mode

’h3037

’h00

Bit[6:5]: PHY bit mode

2’h0: 8-bit mode

2’h1: 10-bit mode

2’h2: 12-bit mode

MIPI clock setting

16’h303f

’h01

Bit[7]: pclk sel

1’h0: sel pll_pclk

MIPI driving

16’h3651

’h7d

Bit[3:0]: MIPI

driving capability, the default value is 4’hd

MIPI Lane 0 delay

16’h3652

’h00

Bit[3]: Lane 0 invert, the default value is

1’h0

Bit[2:0]: Delay of lane 0 equals to the value of bit[2:0] ×

40 ps, the default value is

3’h0

MIPI Lane 1 delay

16’h3652

’h00

Bit[7]: Lane 1 invert, the default value is

1’h0

Bit[6:4]: Delay of lane 1 equals to the value of bit[6:4] ×

40 ps, the default value is

3’h0

MIPI Lane 2 delay

16’h3653

’h00

Bit[3]: Lane 2 invert, the default value is

1’h0

Bit[2:0]: Delay of lane 2 equals to the value of bit[2:0] ×

40 ps, the default value is

3’h0

MIPI Lane 3 delay

16’h3653

’h00

Bit[7]: Lane 3 invert, the default value is

1’h0

Bit[6:4]: Delay of lane 3 equals to the value of bit[6:4] ×

40 ps, the default value is

3’h0

MIPI Clock delay

16’h3654

’h00

Bit[3]: Clock invert, the default value is

1’h0

Bit [2:0]: Delay of MIPI clock equals to the value of bit

[2:0] × 40 ps. The default value is

3’h0.

511820003 Datasheet(PDF) 31 Page - OSRAM GmbH

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