M32CSLASH8B datasheet(114/406 Pages) RENESAS

114 / 406 page

Under development

M32C/8B Group

11. Interrupts

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 97 of 385

11.3

Hardware Interrupts

Special interrupts and peripheral function interrupts are available as hardware interrupts.

11.3.1

Special Interrupts

Special interrupts are non-maskable.

11.3.1.1

NMI Interrupt

The NMI interrupt occurs when a signal applied to the NMI pin changes from high level (“H”) to low level

(“L”). Refer to 11.8 NMI Interrupt for details.

11.3.1.2

Watchdog Timer Interrupt

The watchdog timer interrupt occurs when the watchdog timer counter underflows. Refer to 12. Watchdog

Timer for details.

11.3.1.3

Oscillation Stop Detection Interrupt

The oscillation stop detection interrupt occurs when the MCU detects a loss of the main clock. Refer to 9.

Clock Generation Circuits for details.

11.3.1.4

Voltage Monitor Interrupt

The voltage monitor interrupt occurs when voltage monitor function detects the changes in voltage.

Refer to 6. Power Supply Voltage Monitor Function for details.

11.3.1.5

Single-Step Interrupt

Do not use the single-step interrupt. This is for use with development support tool only.

11.3.1.6

Address Match Interrupt

When the AIERi bit in the AIER register is set to 1 (address match interrupt enabled), the address match

interrupt occurs immediately before executing the instruction stored in the address indicated by the RMADi

Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur if

a table data or any address other than the starting address of the instruction is set. Refer to 11.10 Address

Match Interrupt for details.

11.3.1.7

DMACII End-of-Transfer Complete Interrupt

The DMACII transfer complete interrupt is generated by the DMACII function. Refer to 14. DMACII for

details.

11.3.2

Peripheral Function Interrupt

The peripheral function interrupt is generated by the on-chip peripheral functions. The peripheral function

interrupts and software interrupt numbers 8 to 43 for the INT instruction use the same interrupt vector table.

The peripheral function interrupt is maskable.

See Tables 11.2 and 11.3 for the peripheral function interrupt sources. Refer to the descriptions of individual

peripheral functions for details.

M32C/8B Datasheet(PDF) 114 Page - Renesas Technology Corp

M32C/8B Datasheet(HTML) 114 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL