M32CSLASH8B datasheet(124/406 Pages) RENESAS

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M32C/8B Group

11. Interrupts

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 107 of 385

11.6.4

Interrupt Response Time

Figure 11.7 shows the interrupt response time. Interrupt response time is the period between an interrupt request

generation and the end of an interrupt sequence. Interrupt response time is divided into two phases: the period

between an interrupt request generation and the end of the ongoing instruction execution ((a) in Figure 11.7),

and the period required to perform the interrupt sequence ((b) in Figure 11.7).

Figure 11.7

Interrupt Response Time

Time (a) varies depending on an instruction being executed. The DIV, DIVX, and DIVU instructions require the

longest time (a), which is at the maximum of 42 cycles.

Table 11.5 lists time (b).

Table 11.5

Interrupt Sequence Execution Time(1)

NOTE:

1. The values when interrupt vectors are allocated in even addresses in the internal ROM, except for the high-

speed interrupt.

Interrupts

Execution Time

(in terms of CPU clock)

Peripheral function

14 cycles

INT instruction

12 cycles

NMI

Watchdog timer

Undefined instruction

Address match

13 cycles

Overflow

14 cycles

BRK instruction (relocatable vector table)

17 cycles

BRK instruction (fixed vector table)

19 cycles

High-speed interrupt

5 cycles

Instruction

Interrupt sequence

Instruction in interrupt routine

Time

Interrupt response time

(a)

(b)

Interrupt request is

acknowledged

Interrupt request is

generated

(a) Period between an interrupt request generation and the end of instruction execution.

(b) Period required to perform an interrupt sequence.

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