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M32C/8B Datasheet(PDF) 126 Page - Renesas Technology Corp |
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M32C/8B Datasheet(HTML) 126 Page - Renesas Technology Corp |
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126 / 406 page ![]() Under development M32C/8B Group 11. Interrupts Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 109 of 385 11.6.7 Returning from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the values of the FLG register and PC, which have been saved to the stack before the interrupt sequence is performed, are automatically restored. And then, the program that was running before an interrupt request was acknowledged, resumes its process. The high-speed interrupt uses the FREIT instruction instead. Refer to 11.4 High-Speed Interrupt for details. Before executing the REIT or FREIT instruction, use the POPM instruction or the like to restore registers saved by a program in the interrupt routine. By executing the REIT or FREIT instruction, register bank is switched back to the bank used immediately before the interrupt sequence. 11.6.8 Interrupt Priority If two or more interrupt requests are detected at the same sampling points (a timing to check whether any interrupt request is generated or not), the interrupt with the highest priority is acknowledged. Set bits ILVL2 to ILVL0 in the Interrupt Control Register to select the given priority level for maskable interrupts (peripheral function interrupts). Priority levels of special interrupts, such as NMI and watchdog timer interrupt are fixed by hardware. Figure 11.9 shows the priority of hardware interrupts. The interrupt priority does not affect software interrupts. Executing an instruction for a software interrupt causes the MCU to execute an interrupt routine. Figure 11.9 Interrupt Priority of Hardware Interrupts 11.6.9 Interrupt Priority Level Decision Circuit The interrupt priority level decision circuit selects the highest priority interrupt when two or more interrupt requests are generated at the same sampling point. Figure 11.10 shows the interrupt priority level decision circuit. H L NMI Watchdog timer Oscillation stop detection Voltage monitor Peripheral function Address match |
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