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M32C/8B Datasheet(PDF) 161 Page - Renesas Technology Corp |
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M32C/8B Datasheet(HTML) 161 Page - Renesas Technology Corp |
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161 / 406 page  Under development M32C/8B Group 15. Timer A Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 144 of 385 Figure 15.4 TCSPR Register b7 b6 b5 b4 b1 b2 b3 Symbol TCSPR Address 035Fh After Reset(2) 0XXX 0000b b0 Function Bit Symbol Bit Name RW RW CNT3 Count Source Prescaler Register CNT1 RW RW CNT2 CNT0 RW − (b6-b4) − RW CST If the setting value is n, f2n is the main clock, on-chip oscillator, or PLL clock divided by 2n. No division if n = 0 Divide ratio select bits(1) Read as undefined value 0: Divider stops 1: Divider operates Operation enable bit NOTES: 1. Set the CST bit to 0 before bits CNT3 to CNT0 are rewritten. 2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed. Reserved bits |
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