M32CSLASH8B datasheet(158/406 Pages) RENESAS

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Under development

M32C/8B Group

15. Timers

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 141 of 385

15. Timers

The M32C/8B Group has eleven 16-bit timers, and they are separated into five timer A and six timer B based on their

functions. Individual timers function independently. The count source for each timer is used to operate the timer for

counting and reloading, etc.

Figures 15.1 and 15.2 show block diagrams of timer A and timer B configurations.

Figure 15.1

Timer A Configuration

Timer A3

XCIN

Clock Prescaler

1/32

Set the CPSR bit in the

CPSRF register to 1

Reset

TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TAiMR register

TAiGH, TAiGL: Bits in the ONSF register or the TRGSR register ( i = 0 to 4)

fC32

Timer A0

Timer A1

Timer A2

Timer A4

Timer A0 interrupt

Timer A1 interrupt

Timer A2 interrupt

Timer A3 interrupt

Timer A4 interrupt

TCK1 and TCK0

f1 f8 f2n fC32

TA0IN

TA1IN

TA2IN

TA3IN

TA4IN

TCK1 and TCK0

Timer B2 overflow

or underflow signal

TMOD1 and TMOD0

00: Timer mode

10: One-shot timer mode

11: PWM mode

01: Event counter mode

00: Timer mode

10: One-shot timer mode

11: PWM mode

01: Event counter mode

00: Timer mode

10: One-shot timer mode

11: PWM mode

01: Event counter mode

00: Timer mode

10: One-shot timer mode

11: PWM mode

01: Event counter mode

00: Timer mode

10: One-shot timer mode

11: PWM mode

01: Event counter mode

TA0TGH and TA0TGL

TMOD1 and TMOD0

TA1TGH and TA1TGL

TMOD1 and TMOD0

TA3TGH and TA3TGL

TMOD1 and TMOD0

TA4TGH and TA4TGL

TMOD1 and TMOD0

TA2TGH and TA2TGL

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