M32CSLASH8B datasheet(155/406 Pages) RENESAS

155 / 406 page

Under development

M32C/8B Group

14. DMACII

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 138 of 385

14.3.2

Immediate Data Transfer

DMACII transfers immediate data to a given memory location. A fixed or incremented address can be selected

as a destination address. Store immediate data into SADR. To transfer an 8-bit immediate data, write data in the

low-order byte of SADR. (The high-order byte is ignored.)

14.3.3

Calculation Transfer

After two memory data, or an immediate data and a memory data, are added together, DMACII transfers the

calculated result to a given memory location. Set a memory address or immediate data to be calculated in

SADR. Set another memory address to be calculated in OADR. To use a “memory + memory” calculation

transfer, a fixed or incremented address can be selected as a source or destination address. If a source address is

incremented, an operation address also becomes incremented. To use an “immediate data + memory”

calculation transfer, a fixed or incremented address can be selected as a destination address.

14.4

Transfer Modes

In DMACII, a single transfer, burst transfer, and multiple transfer are available. The BRST bit in MOD selects

either a single transfer or burst transfer, and the MULT bit in MOD selects a multiple transfer. COUNT determines

how many transfers occur. No transfer occurs when COUNT is set to 0000h.

14.4.1

Single Transfer

For one transfer request, DMACII transfers an 8-bit or 16-bit data once. When an incremented address is

selected for a source or destination address, DMACII increments the address after every transfer for the

following transfer.

COUNT is decremented every time a transfer occurs. If using the end-of-transfer interrupt, an interrupt occurs

when COUNT reaches zero.

14.4.2

Burst Transfer

For one transfer request, DMACII continuously transfers data the number of times determined by COUNT.

COUNT is decremented every time DMACII transfers one transfer unit, and when it reaches zero, a burst

transfer is completed. If using the end-of-transfer interrupt, an interrupt occurs at the end of the burst transfer.

While the burst transfer is taking place, no interrupt can be acknowledged.

14.4.3

Multiple Transfer

When using the multiple transfer, select the memory-to-memory transfer. For one transfer request, DMACII

transfers data multiple times. Bits CNT2 to CNT0 in MOD selects the number of transfers from 001b (once) to

111b (7 times). Do not set bits CNT2 to CNT0 to 000b.

Source and destination addresses enough for all transfers must be allocated alternately in addresses following

MOD and COUNT in DMACII index.

While the transfers are taking place the number of times set using bits CNT2 to CNT0, no interrupt can be

acknowledged. When the multiple transfer is selected, a calculation transfer, burst transfer, chain transfer, and

end-of-transfer interrupt cannot be used.

M32C/8B Datasheet(PDF) 155 Page - Renesas Technology Corp

M32C/8B Datasheet(HTML) 155 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL