M32CSLASH8B datasheet(183/406 Pages) RENESAS

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M32C/8B Group

15. Timer B

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 166 of 385

15.2

Timer B

Timer B contains the following three modes. Bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 5)

determine which mode is used.

• Timer mode: The timer counts the internal count source.

• Event counter mode: The timer counts overflows/underflows of another timer, or the external pulses.

• Pulse period measurement mode, pulse width measurement mode: The timer measures the pulse period or

pulse width of the external signal.

Figure 15.21 shows a block diagram of timer B. Figures 15.22 to 15.26 show the registers associated with timer B.

Table 15.8 shows TBiIN pin settings (i = 0 to 5).

Figure 15.21

Timer B Block Diagram

Reload register

Clock source select

TBiS

High-order bits of data bus

Low-order bits of data bus

8 low-order

bits

8 high-order

bits

TBiIN

01: Event counter mode

00: Timer mode

10: Pulse period and pulse

width measurement mode

TMOD1 and TMOD0

TCK1 and TCK0

i= 0 to 5

j = i - 1, except j = 2 if i = 0, j = 5 if i = 3.

NOTES:

1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or

divide-by-2n (n = 1 to 15).

2. Overflow signal or underflow signal.

TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register

TBiS: Bit in the TABSR register or the TBSR register

TBi

Addresses

TBj

Timer B0

0351h

0350h

Timer B2

Timer B1

0353h

0352h

Timer B0

Timer B2

0355h

0354h

Timer B1

Timer B3

0311h

0310h

Timer B5

Timer B4

0313h

0312h

Timer B3

Timer B5

0315h

0314h

Timer B4

f2n(1)

fC32

Counter

TBj overflow(2)

Polarity switching

and edge pulse

Counter reset circuit

TCK1

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