M32CSLASH8B datasheet(185/406 Pages) RENESAS

185 / 406 page

Under development

M32C/8B Group

15. Timer B

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 168 of 385

Figure 15.23

TB0MR to TB5MR Registers in Event Counter Mode

b3 b2

0 0: Falling edges of an external signal counted

0 1: Rising edges of an external signal counted

1 0: Falling and rising edges of an external

signal counted

1 1: Do not set to this value

b6 b5 b4

Symbol

TB0MR to TB5MR

Address

035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh

After Reset

00XX 0000b

Function

Bit Symbol

Bit Name

MR3

TCK1

−

MR1

TCK0

Timer Bi Mode Register (i = 0 to 5)(Event Counter Mode)

TMOD1

MR0

b1 b0

0 1: Event counter mode

Operating mode select bits

TMOD0

Disabled in event counter mode.

Write 0. Read as undefined value.

NOTES:

1. Bits MR1 and MR0 are enabled when the TCK1 bit is set to 0. Bits MR1 and MR0 can be set to either 0 or 1 when the TCK1 bit

is set to 1.

2. j = i - 1, except j = 2 if i = 0 and j = 5 if i = 3.

MR2

−

Registers TB0MR and TB3MR:

Set to 0 in event counter mode.

Registers TB1MR, TB2MR, TB4MR, and TB5MR:

Unimplemented.

Write 0. Read as undefined value.

Count polarity select bits(1)

Disabled in event counter mode.

Can be set to either 0 or 1

0: Signal applied to the TBiIN pin

1: TBj overflows or underflows(2)

Event clock select bit

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