7643 datasheet(368/424 Pages) RENESAS

368 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 45 of 98

Fig. 3.5.3 Structure of Interrupt request register A

Interrupt request register A

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt request register A

(IREQA : address 0216)

Name

Functions

At reset R W

USB function interrupt

request bit

INT1 interrupt request bit

DMAC0 interrupt request

bit

UART receive buffer full

interrupt request bit

INT0 interrupt request bit

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

DMAC1 interrupt request

bit

UART transmit interrupt

request bit

✽

✽: “0” can be set by software, but “1” cannot be set.

Nothing is arranged for this bit. When this bit is read out, the contents

are undefined. This bit is “0” at write.

Interrupt request register B

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt request register B

(IREQB : address 0316)

Name

Functions

At reset R W

UART summing error

interrupt request bit

Timer 1 interrupt request

bit

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

Timer 2 interrupt request

bit

✽

✽: “0” can be set by software, but “1” cannot be set.

Nothing is arranged for these bits.

When these bits are read out, the contents are undefined.

These bits are “0” at write.

Fig. 3.5.4 Structure of Interrupt request register B

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