7643 datasheet(388/424 Pages) RENESAS

388 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 65 of 98

Fig. 3.5.35 Structure of DMAC channel x transfer count registers Low, High (x = 0, 1)

DMAC channel x transfer count registers Low, High

b7 b6 b5 b4 b3 b2 b1 b0

DMAC channel x transfer count registers Low

(DMAxCL : address 4616)

Functions

At reset R W

qThis is the lower 8-bit register with a latch. Set the lower 8 bits of

transfer numbers.

qThis register indicates the remaining transfer numbers while

transfer is continuing.

qThis contents are decreased by 1 at every transfer operation.

qWhen this register underflows, the DMAC interrupt request bit and

the count register underflow flag (Note 2) are set to “1”.

b7 b6 b5 b4 b3 b2 b1 b0

DMAC channel x transfer count registers High

(DMAxCH : address 4716)

Functions

At reset R W

qThis is the higher 8-bit register with a latch. Set the higher 8 bits of

transfer numbers.

qThis register indicates the remaining transfer numbers while

transfer is continuing.

qThis contents are decreased by 1 at every transfer operation.

Notes 1: DMAC channel x transfer count registers low, high of channels 0 and 1 are

assigned at the same addresses 4616 and 4716. The accessible channel depends

on channel index bit, bit 7 of DMAC index and status register.

2: Channel 0 used: Bit 0 of DMAC index and status register

Channel 1 used: Bit 2 of DMAC index and status register

3: Write data into the lower byte first, and then the higher byte.

4: Read the contents from the higher byte first, and then the lower byte.

7643 Datasheet(PDF) 388 Page - Renesas Technology Corp