7643 datasheet(384/424 Pages) RENESAS

384 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 61 of 98

Fig. 3.5.30 Structure of DMAC channel x mode register 1 (x = 0, 1)

DMAC channel x mode register 1 (x = 0, 1)

b7 b6 b5 b4 b3 b2 b1 b0

DMAC channel x mode register 1

(DMAxM1 : address 4016) (Note 1)

Name

Functions

At reset R W

0 : Increment after transfer

1 : Decrement after transfer

0 : Disabled (No change after transfer)

1 : Enabled

DMAC channel x source

selection bit (DxSRID)

DMAC channel x source

enable bit (DxSRCE)

0 : Increment after transfer

1 : Decrement after transfer

0 : Disabled (No change after transfer)

1 : Enabled

DMAC channel x destination

selection bit (DxDRID)

DMAC channel x destination

enable bit (DxDRCE)

DMAC channel x data

write control bit (DxDWC)

0 : Writing data in reload latches and

registers

1 : Writing data in reload latches only

DMAC channel x disable after

count register underflow

enable bit (DxDAUE)

0 : Channel x enabled after count

1 : Channel x disabled after count

DMAC channel x register

reload bit (DxRLD)

0 : Not reloaded

1 : Source, destination, and transfer

count registers contents of channel x

to be reloaded

DMAC channel x transfer

mode selection bit (DxTMS)

0 : Cycle steal transfer mode

1 : Burst transfer mode

(Note 2)

Notes 1: Channels 1 and 2 share this register. The channel selection which can use this register

depends on channel index bit, bit 7 of DMAC index and status register.

2: These bits’ contents are “0” at read.

7643 Datasheet(PDF) 384 Page - Renesas Technology Corp

7643 Datasheet(HTML) 384 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL