7643 datasheet(381/424 Pages) RENESAS

381 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 58 of 98

Fig. 3.5.27 Structure of UART transmit/receive buffer registers 1, 2

UART transmit/receive buffer registers 1, 2

b7 b6 b5 b4 b3 b2 b1 b0

UART transmit/receive buffer register 1

(UTRB1: address 3416)

Undefined

Functions

At reset R W

Undefined

The transmit buffer register and the receive buffer register are located

at the same address. Writing a transmitting data and reading a

received data are performed through the UTRB. This is its low-order

byte.

•At write

The data is written into the transmit buffer register. It is not done into

the receive buffer register.

•At read

The contents of receive buffer register is read.

If a character bit length is 7 bits, the MSB of received data is invalid.

Note that the contents of transmit buffer register cannot be read.

b7 b6 b5 b4 b3 b2 b1 b0

UART transmit/receive buffer register 2

(UTRB2: address 3516)

Undefined

Functions

At reset R W

Undefined

The transmit buffer register and the receive buffer register are located

at the same address. Writing a transmitting data and reading a

received data are performed through the UTRB. This is its high-order

byte.

•At write

The data is written into the transmit buffer register. It is not done into

the receive buffer register.

•At read

The contents of receive buffer register is read.

If a character bit length is 9 bits, the received high-order 7 bits of

UTRB2 are “0”

Note that the contents of transmit buffer register cannot be read. If a

character bit length is 7 or 8 bits, the received contents of UTRB2 are

invalid.

Nothing is arranged for these bits. These are write disable bits.

When these bits are read out, the contents are “0”.

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