7643 datasheet(378/424 Pages) RENESAS

378 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 55 of 98

Serial I/O control register 2

b7 b6 b5 b4 b3 b2 b1 b0

Serial I/O control register 2

(SIOCON2 : address 2C16)

00 0

Name

Functions

At reset R W

Clock polarity select bit

(CPoL)

Clock phase select bit

(CPha)

SRXD input enable bit

0 : Normal serial I/O mode

1 : SPI compatible mode (Note)

0 : SRXD input disabed

1 : SRXD input enabed

0 : SCLK starting at “L”

1 : SCLK starting at “H”

0 : Serial transfer starting at falling edge

of SRDY

1 : Serial transfer starting after a half

cycle of SCLK passed at falling edge

of SRDY

SPI mode select bit

Nothing is arranged for these bits.

Fix these bits to “0”.

Note: To set the slave mode, also set bit 4 of serial I/O control register 1 to “1”.

Nothing is arranged for this bit.

Fix this bit to “0”.

Fig. 3.5.22 Structure of Serial I/O control register 2

Serial I/O control register 1

b7 b6 b5 b4 b3 b2 b1 b0

Serial I/O control register 1

(SIOCON1 : address 2B16)

Name

Functions

At reset R W

SRDY output select bit

Transfer direction select bit

Serial I/O port select bit

b2b1b0

0 0 0 :

φ/2

0 0 1 :

φ/4

0 1 0 :

φ/8

0 1 1 :

φ/16

1 0 0 :

φ/32

1 0 1 :

φ/64

1 1 0 :

φ/128

1 1 1 :

φ/256

0 : I/O port

1 : STXD, SCLK signal output

0 : I/O port

1 : SRDY signal output

Synchronous clock select

bit

STXD output channel

control bit

Internal synchronous clock

select bits

(Note)

0 : LSB first

1 : MSB first

0 : External input (SCLK pin input)

1 : Internal synchronous clock

0 : CMOS output

1 : N-channel open drain output

Note: The source of serial I/O internal sysnchronous clock can be selected

by bit 1 of serial I/O control register 2.

Fig. 3.5.21 Structure of Serial I/O control register 1

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